`timescale  1 ns/1 ps

module test
(
    input                       clk_p,
    input                       clk_n,
    input                       rst_n,

    //--------------- MII Interface
    output                      phy_resetn,
    output                      gmii_tx_clk,
    output       [07:00]        gmii_txd,
    output                      gmii_tx_en,
    output                      gmii_tx_er,
    input                       gmii_rx_clk,
    input        [07:00]        gmii_rxd,
    input                       gmii_rx_dv,
    input                       gmii_rx_er      
);

wire                        clk_10m;
wire                        clk_125m;
wire                        clk_200m;
wire                        locked;


wire [07:00]                load_m_axi_tdata;
wire                        load_m_axi_tvalid;
wire                        load_m_axi_tready;
wire                        load_m_axi_tlast;

  clk_wiz_0 instance_name
   (
    // Clock out ports
    .clk_out1               (  clk_10m                         ),
    .clk_out2               (  clk_125m                        ),
    .clk_out3               (  clk_200m                        ),
    // Status and control signals
    .resetn                 (  rst_n                           ),
    .locked                 (  locked                          ),
   // Clock in ports
    .clk_in1_p              (  clk_p                           ),
    .clk_in1_n              (  clk_n                           ));

enthernet_top #
(
    .C_CLK_FREQ_HZ          (  125_000_000                     ),
    .LOCAL_MAC_ADDR         (  48'hC400C4010102                ),
    .LOCAL_IP_ADDR          (  {8'd192,8'd168, 8'd1,8'd102}    ),
    .LOCAL_UDP_PORT         (  16'd4444                        ),
    .REMOTE_UDP_PORT        (  16'd6666                        )
)
enthernet_topEx01
(
    .clk                    (  clk_125                         ),
    .clk_200m               (  clk_200m                        ),
    .rst                    (  rst                             ),
    .load_parameter         (                                  ),
    .load_m_axi_tdata       (  load_m_axi_tdata                ),
    .load_m_axi_tvalid      (  load_m_axi_tvalid               ),
    .load_m_axi_tready      (  1'b1               ),
    .load_m_axi_tlast       (  load_m_axi_tlast                ),
    .update_paramter        (  32'd0                           ),
    .update_m_axi_tdata     (  update_m_axi_tdata              ),
    .update_m_axi_tvalid    (  update_m_axi_tvalid             ),
    .update_m_axi_tready    (                                  ),
    .update_m_axi_tlast     (  update_m_axi_tlast              ),
    .phy_resetn             (  phy_resetn                      ),
    .gmii_tx_clk            (  gmii_tx_clk                     ),
    .gmii_txd               (  gmii_txd                        ),
    .gmii_tx_en             (  gmii_tx_en                      ),
    .gmii_tx_er             (  gmii_tx_er                      ),
    .gmii_rx_clk            (  gmii_rx_clk                     ),
    .gmii_rxd               (  gmii_rxd                        ),
    .gmii_rx_dv             (  gmii_rx_dv                      ),
    .gmii_rx_er             (  gmii_rx_er                      )
);


ila_0 ila_0Ex01 (
	.clk(clk_125m), // input wire clk


	.probe0({load_m_axi_tdata, load_m_axi_tvalid, load_m_axi_tlast, gmii_rxd, gmii_rx_dv, gmii_rx_er, 44'd0}) // input wire [63:0] probe0
);
endmodule
